In order to improve the output of integrated circuits, fabricators have increased the number of transistors on the circuit substrate by increasing its surface area by means of fins, usually formed from the same material as the substrate, and projecting upwardly from the surface. Selectively doping regions of the fins produces transistor structures.
The FIN structure provides a tri-gate (gate on both FIN sides and FIN top) structure. This tri-gate structure has better electrostatic control for a short-channel FET, in comparison to conventional planar devices. On other hand, it can provide more effective channel width per area than planar devices, i.e., it is more efficient than planar devices from an area scaling perspective.
This is part of the “silicon revolution” that drove the development of faster and larger computers beginning in the early 1960's giving rise to predictions of rapid growth because of the increasing numbers of transistors packed into integrated circuits with estimates they would double every two years. Since 1975, however, they doubled about every 18 months.
An active period of innovation in the 1970's followed in the areas of circuit design, chip architecture, design aids, processes, tools, testing, manufacturing architecture, and manufacturing discipline. The combination of these disciplines brought about the VLSI era and the ability to mass-produce chips with 100,000 transistors per chip at the end of the 1980's, succeeding the large scale Integration (“LSI”) era of the 1970's with only 1,000 transistors per chip. (Carre, H. et al. “Semiconductor Manufacturing Technology at IBM”, IBM J. RES. DEVELOP., VOL. 26, no. 5, September 1982). Mescia et al. also describe the industrial scale manufacture of these VLSI devices. (Mescia, N.C. et al. “Plant Automation in a Structured Distributed System Environment,” IBM J. RES. DEVELOP., VOL. 26, no. 4, (July 1982).
The release of IBM's Power6™ chip in 2007, noted “miniaturization has allowed chipmakers to make chips faster by cramming more transistors on a single slice of silicon, to the point where high-end processors have hundreds of millions of transistors . . . .” (http://www.nytimes.com/reuters/technology/tech-ibm-power.html?pagewanted=print (Feb. 7, 2006))
More recently, “engineers did a rough calculation of what would happen had a 1971 Volkswagen Beetle improved at the same rate as microchips did under Moore's Law: ‘Here are the numbers: [Today] you would be able to go with that car 300,000 miles per hour. You would get two million miles per gallon of gas, and all that for the mere cost of 4 cents!’” T. Friedman, N.Y. Times, Op Ed, May 13, 2015.
Technology scaling of semiconductor devices to 90 nm and below has provided many benefits in the field of microelectronics, but has introduced new considerations as well. While smaller chip geometries result in higher levels of on-chip integration and performance, higher current and power densities, increased leakage currents, and low-k dielectrics that present new challenges to package designs.
The FinFET transistor evolved from these considerations. It has at least one thin portion, referred to as the “fin,” comprising a semiconductor material that defines the elongated section to form the channel of the transistor and also includes source and drain zones. In the process, a mask formed on top of a monocrystalline silicon substrate defines the fin and its position. Once defined, etching the substrate material directionally around the mask, to a determined depth, allows the elongated section defining the fin to remain under the mask and retain its composition as substrate material.
Some integrated circuits employ one or more FinFET type field effect transistors having a channel region oriented to conduct an electrical current parallel to the surface of the transistor substrate. The channel region sits in an elongated section of semiconductor material referred to as a fin with the elongated section located on either side of the channel. It usually includes the source and drain regions of the transistor. Positioning a gate over and on both opposed sides of the elongated section at the location of the channel provides a means to control the transistor's conductive state. Intermediate gate portions of the transistor gate span the multiple elongated sections perpendicular to the neighboring channel regions and separate them. Fabricators use this FinFET design for manufacturing multi-channel transistors with multiple elongated sections formed in parallel to define neighboring channel regions.
This semiconductor material fin (a FinFET), comprises the channel of the final transistor, but is not electrically insulated from the active portion of the crystalline semiconductor material circuit substrate. This device suffers from three distinct types of leakage current: first, a type of leakage current, internal to each transistor, that can circulate between the source and drain of the FinFET transistor via the active portion of the substrate situated below the channel; the potential applied to the transistor gate does not control this; second, a type of leakage current develops because the channel of the FinFET transistor is also in electrical contact, via the substrate, with the channels of other transistors of the same conductivity type; in the second, leakage current flows between transistors in the form of an inter-transistor leakage current; and third, leakage current appears between the channel of each FinFET transistor and a lower part of the substrate in response to the substrate being connected to a reference potential.
Bottom oxidation through STIs (BOTS), however, allows for dielectrically isolating the fin by forming shallow trench isolation (STI) structures on either side of the fin. The silicon material of the fin is protected on a top side by a silicon nitride oxygen barrier layer and the upper lateral sides of the fin are isolated from the STI structures by another silicon nitride oxygen barrier layer, followed by an oxidation process to convert a lower unmasked, i.e., unprotected, portion of the fin below the lateral barrier layers to a thermal oxide material which isolates the upper portion of the fin from the underlying substrate material. This, however, produces an undesirable scalloped interface shape at the bottom of the fin, inherent in thermal oxide growth. Also, the process does not work well with fins made from silicon-germanium (SiGe) and does not readily lend itself to forming p-channel SiGe FinFET devices.
A related so-called “silicon on nothing (SON)” process forms the bottom portion of a fin from silicon-germanium and the upper portion from silicon. This involves removing the silicon-germanium bottom portion by selective etching to open a region between the underside of the Si fin and the underlying substrate followed by filling the opened region with an insulating material; however, in many instances this not only produces Si fins with unacceptable mechanical stability, but also results in incomplete fill of the opened region with the insulating material, i.e., tunnel fill issues.
FinFET transistors formed on Silicon-on-Insulator (SOI) integrated circuit substrates in lieu of bulk semiconductor substrates address leakage currents. SOI substrates comprise three layers; a top semiconductor layer, e.g., Si or Ge; an insulating intermediate layer; and a bottom semiconductor substrate layer such as a Si layer. The intermediate layer electrically insulates the transistor from the lower part of the substrate to substantially minimize or substantially eliminate these leakage currents
Processing innovations have produced transistor fabrication substrates with a reduced intervening insulating layer thickness, about 50 nm, referred to as an extremely thin silicon on insulator (ETSOI) substrate. Further development reduced substrate thicknesses to now produce an intervening insulating layer about 25 nm or less and the top semiconductor layer about 5 nm to 10 nm. Fabricators refer to these as ultra-thin body and buried oxide (UTBB) substrates. All of these substrates comprise SOI substrates.
The FinFET transistor on an SOI substrate provides an excellent platform for fabricating smaller and smaller circuits, especially CMOS integrated circuits. The FinFET transistor allows superior short channel control along with higher performance as compared to conventional planar bulk devices, well recognized by fabricators as advantages of the FinFET for CMOS circuits.
Fabricators form the fin by etching into the bulk circuit substrate, but as noted, the fin profile tends to be tapered at the bottom due to plasma etch fundamental limitations. In BOTS fin formation it would be advantageous, however, to provide a process to form these fins without a tapered fin profile, i.e., to form a shallow fin with a substantially vertical fin sidewall profile.
The FIN width (DFin) has a strong impact on short-channel effect. If the FIN is tapered, i.e., small Dfin at the top but large Dfin at the bottom, the short channel effect is worse for the large Dfin. Thus the overall FIN device (FET) behavior will lose control, resulting in large variations. Therefore a vertical FIN sidewall is very important and required for device manufacturability.